Increase in the size of LSI (Large Scale Integration) requires higher machine performance and larger memory necessary for the execution of EDA (Electronic Design Automation) tools, which makes processing of the entire LSI chip at once difficult. Along with the increase in the size of LSI, designing a single LSI on a basis of a part of hierarchically divided circuits (hereinafter referred to as a macro) has become main stream.
On the other hand, speed of LSI has been enhanced. For operating LSI at a high speed, in a case of a synchronization circuit, synchronous operation of flip-flops (FFs) and the like is crucial. It is accordingly essential to suppress variation (clock skews) of delay times of clock signals applied to the respective FFs.
As a method of clock distribution in hierarchical design, common is executing distribution up to one isolated terminal in each macro in top processing, executing further distribution in macro processing and merging clock distribution of the top processing and clock distribution of the macro processing at the time of chip processing as shown in FIG. 11.
This common clock distribution method has a problem that when synchronizing the entire chip, the number of stages will be increased to increase clock skews. More specifically with reference to FIG. 11, clock paths c1 and c2 will have an increased number of stages to increase clock skews because the clock paths c1 and c2 bypass a macro m1 to lead to macros m2 and m3.
The necessity has arisen in recent years for adopting such a clock distribution method as shown in FIG. 12 of executing clock distribution on the entire surface of a chip in top processing and executing macro processing by taking out, from clock paths distributed on the entire surface of the chip, a part of clock paths existing in a macro.
As related art here, Patent Literature 1 discloses the invention of merging a top netlist and a low-order hierarchy netlist (macro netlist) to generate an entire chip netlist including the entire LSI with wiring RC information of a macro boundary merged.
Patent Literature 1: Japanese Patent Laying-Open No. 2003-296392
Patent Literature 2: Japanese Patent Laying-Open No. 2001-273338
Patent Literature 3: Japanese Patent Laying-Open No. 2006-039621
Patent Literature 4: Japanese Patent Laying-Open No. 2007-188517
Patent Literature 5: Japanese Patent Laying-Open No. 2000-243846
Patent Literature 6: Japanese Patent Laying-Open No. 2000-223578
Patent Literature 7: Japanese Patent Laying-Open No. 2000-172738
Patent Literature 8: Japanese Patent Laying-Open No. 2000-100948
Patent Literature 9: Japanese Patent Laying-Open No. 2000-259686
Patent Literature 10: Japanese Patent Laying-Open No. 2000-305966
Patent Literature 11: Japanese Patent Laying-Open No. 2000-250950
Patent Literature 12: Japanese Patent Laying-Open No. 2008-9787
Patent Literature 13: Japanese Patent Laying-Open No. 2005-23534
In a case of processing a macro, the clock distribution method of executing processing by taking out, from clock paths distributed on the entire surface of a chip, a part of clock paths existing in the macro disables a circuit (including a clock path) outside a macro as shown in FIG. 13 to be recognized in a timing analysis tool, so that timing analysis of a macro boundary path (UNIT boundary path) is impossible (no macro boundary path can be analyzed before chip processing is executed).
As a result, there is a problem that in order to prevent a macro boundary path from having a timing error at the time of chip processing, macro processing needs to consider an unnecessarily large design margin. Further problem is large backtracking when a macro boundary path causes a timing error as shown in FIG. 14.
In addition, while the invention disclosed in Patent Literature 1 recites merging a top netlist and a low-order hierarchy netlist (macro netlist), it aims at generating a netlist of the entire chip including a macro boundary path, which object is different from that of the present invention. The invention disclosed in Patent Literature 1 executes only rough wiring processing with respect to a low-order hierarchy, so that it is only possible to obtain a delay value different from a real delay value.